#----------------------------------------------------------- # Vivado v2021.2 (64-bit) # SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 # Start of session at: Sun Apr 12 14:20:43 2026 # Process ID: 35455 # Current directory: /home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1 # Command line: vivado -log system_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace # Log file: /home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper.vdi # Journal file: /home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/vivado.jou # Running On: debian, OS: Linux, CPU Frequency: 697.418 MHz, CPU Physical cores: 4, Host memory: 16490 MB #----------------------------------------------------------- source system_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/radio76/Documents/red-pitaya-notes/tmp/cores'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2021.2/data/ip'. Command: link_design -top system_wrapper -part xc7z020clg400-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7z020clg400-1 Netlist sorting complete. Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2591.383 ; gain = 0.000 ; free physical = 905 ; free virtual = 3034 INFO: [Netlist 29-17] Analyzing 840 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2021.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0_board.xdc] for cell 'system_i/pll_0/inst' Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0_board.xdc] for cell 'system_i/pll_0/inst' Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0.xdc] for cell 'system_i/pll_0/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0.xdc:57] get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.160 ; gain = 194.844 ; free physical = 269 ; free virtual = 2415 Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0.xdc] for cell 'system_i/pll_0/inst' Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_ps_0_0/system_ps_0_0.xdc] for cell 'system_i/ps_0/inst' Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_ps_0_0/system_ps_0_0.xdc] for cell 'system_i/ps_0/inst' Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_rst_0_0/system_rst_0_0_board.xdc] for cell 'system_i/rst_0/U0' Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_rst_0_0/system_rst_0_0_board.xdc] for cell 'system_i/rst_0/U0' Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_rst_0_0/system_rst_0_0.xdc] for cell 'system_i/rst_0/U0' Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_rst_0_0/system_rst_0_0.xdc] for cell 'system_i/rst_0/U0' Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_fir_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'system_i/fir_0/U0' Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.gen/sources_1/bd/system/ip/system_fir_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'system_i/fir_0/U0' Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/cfg/clocks.xdc] Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/cfg/clocks.xdc] Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc] WARNING: [Vivado 12-584] No ports matched 'Vp_Vn_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:127] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:127] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vp_Vn_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:128] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:128] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux0_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:129] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:129] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux0_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:130] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:130] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux1_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:131] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:131] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux1_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:132] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:132] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux8_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:133] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:133] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux8_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:134] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:134] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux9_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:135] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:135] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux9_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:136] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:136] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vp_Vn_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:138] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:138] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vp_Vn_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:139] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:139] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux0_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:140] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:140] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux0_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:141] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:141] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux1_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:142] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:142] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux1_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:143] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:143] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux8_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:144] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:144] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux8_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:145] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:145] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux9_v_p'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:146] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:146] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'Vaux9_v_n'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:147] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:147] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_p_o[*]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:177] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:177] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_n_o[*]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:178] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:178] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_p_i[*]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:180] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:180] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_n_i[*]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:181] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:181] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_p_o[0]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:183] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:183] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_n_o[0]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:184] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:184] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_p_o[1]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:186] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:186] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_n_o[1]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:187] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:187] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_p_i[0]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:189] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:189] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_n_i[0]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:190] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:190] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_p_i[1]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:192] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:192] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. WARNING: [Vivado 12-584] No ports matched 'daisy_n_i[1]'. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:193] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc:193] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/home/radio76/Documents/red-pitaya-notes/cfg/ports.xdc] INFO: [Project 1-1714] 1 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 2 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 313 ; free virtual = 2466 INFO: [Project 1-111] Unisim Transformation Summary: A total of 72 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 64 instances 14 Infos, 32 Warnings, 32 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 3338.402 ; gain = 747.113 ; free physical = 313 ; free virtual = 2466 Command: opt_design -directive ExploreWithRemap INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreWithRemap Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[0] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[1] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[2] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[3] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port exp_p_tri_io[7] expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.54 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 289 ; free virtual = 2447 Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Retarget INFO: [Opt 31-1287] Pulled Inverter system_i/dac_0/inst/int_dat_a_reg[0]_i_1 into driver instance system_i/mult_4/inst/P[0]_INST_0, which resulted in an inversion of 1 pins INFO: [Opt 31-1287] Pulled Inverter system_i/dac_0/inst/int_dat_b_reg[0]_i_1 into driver instance system_i/mult_5/inst/P[0]_INST_0, which resulted in an inversion of 1 pins INFO: [Opt 31-138] Pushed 2 inverter(s) to 8 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 289ece8cd Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 201 ; free virtual = 2246 INFO: [Opt 31-389] Phase Retarget created 8 cells and removed 419 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 257d7d00e Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 198 ; free virtual = 2243 INFO: [Opt 31-389] Phase Constant propagation created 1962 cells and removed 2070 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1ffb44a8d Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 198 ; free virtual = 2243 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 471 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 1ffb44a8d Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 198 ; free virtual = 2243 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 1ffb44a8d Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 198 ; free virtual = 2243 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Remap Phase 6 Remap | Checksum: 2246ac6c7 Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 222 ; free virtual = 2040 INFO: [Opt 31-389] Phase Remap created 48 cells and removed 64 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 1bfd35225 Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 222 ; free virtual = 2040 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 8 | 419 | 1 | | Constant propagation | 1962 | 2070 | 0 | | Sweep | 0 | 471 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Remap | 48 | 64 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 220 ; free virtual = 2043 Ending Logic Optimization Task | Checksum: 1cacf2e03 Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 220 ; free virtual = 2043 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 220 ; free virtual = 2043 Ending Netlist Obfuscation Task | Checksum: 1cacf2e03 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 220 ; free virtual = 2043 INFO: [Common 17-83] Releasing license: Implementation 35 Infos, 40 Warnings, 32 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3338.402 ; gain = 0.000 ; free physical = 220 ; free virtual = 2043 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3358.844 ; gain = 5.938 ; free physical = 199 ; free virtual = 2027 INFO: [Common 17-1381] The checkpoint '/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_drc_opted.rpt. report_drc completed successfully Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 159 ; free virtual = 1959 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11d6b897b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 159 ; free virtual = 1959 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 159 ; free virtual = 1959 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1fa0a980c Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 188 ; free virtual = 1993 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1b9886fb8 Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 208 ; free virtual = 1995 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1b9886fb8 Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 208 ; free virtual = 1995 Phase 1 Placer Initialization | Checksum: 1b9886fb8 Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 208 ; free virtual = 1995 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2472b4217 Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 219 ; free virtual = 2006 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1f23ce462 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 215 ; free virtual = 2007 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f23ce462 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 215 ; free virtual = 2006 Phase 2.4 Global Placement Core Phase 2.4.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 761 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 364 nets or LUTs. Breaked 0 LUT, combined 364 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 169 ; free virtual = 1971 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 364 | 364 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 364 | 364 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.1 Physical Synthesis In Placer | Checksum: 145199a9b Time (s): cpu = 00:00:35 ; elapsed = 00:00:10 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 170 ; free virtual = 1972 Phase 2.4 Global Placement Core | Checksum: 18bf97baf Time (s): cpu = 00:00:36 ; elapsed = 00:00:11 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 173 ; free virtual = 1969 Phase 2 Global Placement | Checksum: 18bf97baf Time (s): cpu = 00:00:36 ; elapsed = 00:00:11 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 179 ; free virtual = 1975 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 16ce240bb Time (s): cpu = 00:00:38 ; elapsed = 00:00:11 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 179 ; free virtual = 1975 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e725a5a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:12 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 177 ; free virtual = 1973 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: a5dd0725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:13 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 175 ; free virtual = 1972 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 9ed14f31 Time (s): cpu = 00:00:42 ; elapsed = 00:00:13 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 175 ; free virtual = 1972 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 15725b604 Time (s): cpu = 00:00:44 ; elapsed = 00:00:14 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 163 ; free virtual = 1966 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 12903396f Time (s): cpu = 00:00:44 ; elapsed = 00:00:14 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 163 ; free virtual = 1966 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 122192628 Time (s): cpu = 00:00:44 ; elapsed = 00:00:14 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 164 ; free virtual = 1967 Phase 3 Detail Placement | Checksum: 122192628 Time (s): cpu = 00:00:44 ; elapsed = 00:00:15 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 164 ; free virtual = 1967 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 176279388 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.038 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 17a5aa25b Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 178 ; free virtual = 1961 INFO: [Place 46-33] Processed net system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net system_i/cic_0/U0/i_synth/decimator.decimation_filter/sclr_int, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net system_i/cic_1/U0/i_synth/decimator.decimation_filter/sclr_int, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 185a83f65 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 173 ; free virtual = 1960 Phase 4.1.1.1 BUFG Insertion | Checksum: 176279388 Time (s): cpu = 00:00:53 ; elapsed = 00:00:17 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 173 ; free virtual = 1960 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=1.038. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1694058c4 Time (s): cpu = 00:00:53 ; elapsed = 00:00:17 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 173 ; free virtual = 1960 Time (s): cpu = 00:00:53 ; elapsed = 00:00:17 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 173 ; free virtual = 1960 Phase 4.1 Post Commit Optimization | Checksum: 1694058c4 Time (s): cpu = 00:00:53 ; elapsed = 00:00:17 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 173 ; free virtual = 1960 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1694058c4 Time (s): cpu = 00:00:53 ; elapsed = 00:00:17 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 4x4| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1694058c4 Time (s): cpu = 00:00:53 ; elapsed = 00:00:18 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 Phase 4.3 Placer Reporting | Checksum: 1694058c4 Time (s): cpu = 00:00:53 ; elapsed = 00:00:18 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 Time (s): cpu = 00:00:53 ; elapsed = 00:00:18 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1760a6529 Time (s): cpu = 00:00:54 ; elapsed = 00:00:18 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 Ending Placer Task | Checksum: e50ea742 Time (s): cpu = 00:00:54 ; elapsed = 00:00:18 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1961 INFO: [Common 17-83] Releasing license: Implementation 74 Infos, 40 Warnings, 32 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:18 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 199 ; free virtual = 1986 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.69 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 174 ; free virtual = 1966 INFO: [Common 17-1381] The checkpoint '/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 189 ; free virtual = 1963 INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 207 ; free virtual = 1981 Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 84 Infos, 40 Warnings, 32 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.70 . Memory (MB): peak = 3537.348 ; gain = 0.000 ; free physical = 165 ; free virtual = 1935 INFO: [Common 17-1381] The checkpoint '/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_physopt.dcp' has been generated. Command: route_design -directive NoTimingRelaxation -tns_cleanup Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'NoTimingRelaxation'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: a93095b5 ConstDB: 0 ShapeSum: 3bde118d RouteDB: 0 Post Restoration Checksum: NetGraph: c29ce403 NumContArr: 32d331b3 Constraints: 0 Timing: 0 Phase 1 Build RT Design | Checksum: f57015b6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 3604.172 ; gain = 34.664 ; free physical = 518 ; free virtual = 2281 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: f57015b6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 3604.172 ; gain = 34.664 ; free physical = 522 ; free virtual = 2286 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: f57015b6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 3631.168 ; gain = 61.660 ; free physical = 479 ; free virtual = 2243 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: f57015b6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 3631.168 ; gain = 61.660 ; free physical = 479 ; free virtual = 2243 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1c804648a Time (s): cpu = 00:00:27 ; elapsed = 00:00:17 . Memory (MB): peak = 3666.301 ; gain = 96.793 ; free physical = 427 ; free virtual = 2192 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.182 | TNS=0.000 | WHS=-0.249 | THS=-358.610| Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 17902 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 17902 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 1c4f3d601 Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 3666.301 ; gain = 96.793 ; free physical = 424 ; free virtual = 2194 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1c4f3d601 Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 3666.301 ; gain = 96.793 ; free physical = 424 ; free virtual = 2194 Phase 3 Initial Routing | Checksum: e6a810bd Time (s): cpu = 00:00:37 ; elapsed = 00:00:20 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 422 ; free virtual = 2192 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 283 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.063 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1063dba7b Time (s): cpu = 00:00:45 ; elapsed = 00:00:22 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 420 ; free virtual = 2190 Phase 4 Rip-up And Reroute | Checksum: 1063dba7b Time (s): cpu = 00:00:45 ; elapsed = 00:00:22 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 420 ; free virtual = 2190 Phase 5 Delay and Skew Optimization Phase 5.1 TNS Cleanup Phase 5.1.1 Delay CleanUp Phase 5.1.1.1 Update Timing Phase 5.1.1.1 Update Timing | Checksum: 16082d26e Time (s): cpu = 00:00:47 ; elapsed = 00:00:23 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 423 ; free virtual = 2193 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.077 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1.1 Delay CleanUp | Checksum: 16082d26e Time (s): cpu = 00:00:47 ; elapsed = 00:00:23 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 423 ; free virtual = 2193 Phase 5.1 TNS Cleanup | Checksum: 16082d26e Time (s): cpu = 00:00:47 ; elapsed = 00:00:23 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 423 ; free virtual = 2193 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 16082d26e Time (s): cpu = 00:00:47 ; elapsed = 00:00:23 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 423 ; free virtual = 2193 Phase 5 Delay and Skew Optimization | Checksum: 16082d26e Time (s): cpu = 00:00:47 ; elapsed = 00:00:23 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 426 ; free virtual = 2196 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 16b29f2da Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 426 ; free virtual = 2196 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.077 | TNS=0.000 | WHS=0.018 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 11b387548 Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 426 ; free virtual = 2196 Phase 6 Post Hold Fix | Checksum: 11b387548 Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 426 ; free virtual = 2196 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 6.16806 % Global Horizontal Routing Utilization = 6.45174 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1910cb518 Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 426 ; free virtual = 2196 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1910cb518 Time (s): cpu = 00:00:49 ; elapsed = 00:00:24 . Memory (MB): peak = 3714.074 ; gain = 144.566 ; free physical = 424 ; free virtual = 2194 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1f7f8c0aa Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3762.098 ; gain = 192.590 ; free physical = 429 ; free virtual = 2198 Phase 10 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.077 | TNS=0.000 | WHS=0.018 | THS=0.000 | Phase 10 Post Router Timing | Checksum: 17a99b1dd Time (s): cpu = 00:00:57 ; elapsed = 00:00:26 . Memory (MB): peak = 3762.098 ; gain = 192.590 ; free physical = 437 ; free virtual = 2207 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:57 ; elapsed = 00:00:26 . Memory (MB): peak = 3762.098 ; gain = 192.590 ; free physical = 558 ; free virtual = 2328 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 100 Infos, 40 Warnings, 32 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:04 ; elapsed = 00:00:28 . Memory (MB): peak = 3762.098 ; gain = 224.750 ; free physical = 558 ; free virtual = 2328 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.72 . Memory (MB): peak = 3762.098 ; gain = 0.000 ; free physical = 513 ; free virtual = 2320 INFO: [Common 17-1381] The checkpoint '/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 8 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 112 Infos, 41 Warnings, 32 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed) INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.87 . Memory (MB): peak = 3784.062 ; gain = 0.000 ; free physical = 367 ; free virtual = 2215 INFO: [Common 17-1381] The checkpoint '/home/radio76/Documents/red-pitaya-notes/tmp/labview_RP.runs/impl_1/system_wrapper_postroute_physopt.dcp' has been generated. INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -warn_on_violation -file system_wrapper_timing_summary_postroute_physopted.rpt -pb system_wrapper_timing_summary_postroute_physopted.pb -rpx system_wrapper_timing_summary_postroute_physopted.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_postroute_physopted.rpt -pb system_wrapper_bus_skew_postroute_physopted.pb -rpx system_wrapper_bus_skew_postroute_physopted.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force system_wrapper.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[0].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[1].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[2].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[3].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[4].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[5].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[6].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer system_i/io_bridge_out/inst/iobufs[7].iobuf_inst/IBUF has no loads. It is recommended to have an input buffer drive an internal load. INFO: [DRC REQP-28] enum_USE_MULT_NONE_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-28] enum_USE_MULT_NONE_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-28] enum_USE_MULT_NONE_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-28] enum_USE_MULT_NONE_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-28] enum_USE_MULT_NONE_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-28] enum_USE_MULT_NONE_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-30] enum_MREG_0_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-30] enum_MREG_0_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-30] enum_MREG_0_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-30] enum_MREG_0_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-30] enum_MREG_0_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-30] enum_MREG_0_connects_CEM_GND: system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power. INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 8 Warnings, 13 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./system_wrapper.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 42 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 3958.324 ; gain = 174.262 ; free physical = 520 ; free virtual = 2274 INFO: [Common 17-206] Exiting Vivado at Sun Apr 12 14:23:00 2026...